Paper Title: Comparison of Current 3D NAND Chip and Cell Architectures

Paper Abstract: Every NAND manufacturer focuses on 3D NAND production. Beyond storage density, 3D NAND is used for even the fastest SSDs, such as Samsung's Z-SSD. Of course, there are differences between the 3D designs. For example, Samsung, Toshiba, WDC and SK Hynix design their own CTL (Charge Trap Layer)-based 3D NAND, namely TCAT V-NAND, BiCS and P-BiCS, respectively. Intel and Micron developed a unique FG (Floating Gate)-based 3D CuA NAND. Amid increasing demand, the major NAND suppliers reached up to 92L and 96L active cells, which means the total number of vertical gates stacked is already over one hundred. For example, Intel/Micron's 106 gates and Toshiba's 109 gates for their 96L 3D NAND products. Bit Density reached up to 6.53 Gb/mm2 with QLC NAND design. These technologies will be compared side-by-side in detail.

Paper Author: Jeongdong Choe, Senior Technical Fellow, TechInsights

Author Bio: Dr. Jeongdong Choe is a Sr Technical Fellow at TechInsights. He has over 28 years of experience in the semiconductor industry, R&D and reverse engineering on DRAM, NAND/NOR FLASH, SRAM/Logic, emerging memory and package. He worked for SK Hynix (old LG Semicon or Goldstar Electronics) and Samsung Electronics for over 20 years. He joined TechInsights and has been leading technical research, reverse engineering, patent analysis and consulting on semiconductor devices. He has written many papers and articles on memory technology including DRAM comparison, 3D NAND details and XPoint design and architecture. He quarterly produces and updates a widely distributed roadmaps for memory technology. He earned a PhD from Sungkyunkwan University in electrical engineering.