Paper Title: TaOx-based ReRAM for Variability-Aware Approximate Computing
Paper Abstract: The bit error rate (BER) of TaOx ReRAM degrades and increases in variability as the storage medium is used. Variability-Aware Approximate Computing (V-AC) utilizes the error resilience of machine learning applications to enhance the ReRAM’s performance. The proposed V-AC reduces BER of typical cells by removing the extra data copying of wear-leveling and by enlarging the BER difference among ReRAM cells. By co-designing the system, circuit, and device, the performance, energy, and cell area of ReRAM storage improves by 7.0 times, 90%, and 8.5%, respectively.
Paper Author: Chihiro Matsui, Assistant Professor, Chuo University/University of Tokyo (Japan)
Author Bio: Chihiro Matsui is an assistant professor at Chuo University. She has been working for non-volatile memory system heterogeneously integrated with emerging non-volatile memoeries and NAND flash. Her research interests are non-volatile memory system design for enterprise applications. She has published several research articles in Proceedings of the IEEE and IEEE Transactions of VLSI.
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