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3:20-5:45 PM
FTEC-202-1: 3-D Flash (Flash Technology Track)
Paper Title: Measuring the Difficulty of Programming 3D NAND

Paper Abstract: The consistency of programming quality in 3D NAND is much worse than that in 2D NAND. There are great complexity and subtle differences between chips, blocks and wordlines (WL). How to accurately measure the quality of programming has become a challenge in evaluating 3D NAND performance. Here, we introduce a set of metrics that can accurately measure the quality of 3D programming. For example, "Valid Window" can be used to measure the distance of adjacent state of XLC. "Central Point Distribution" can be used to measure the stability of programming. These metrics can be used not only to measure the quality of programming, but also to develop read retry tables.

Paper Author: Vic Ye, Manager, YeeStor Microelectronics

Author Bio: Vic Ye is the manager of the Flash Analysis Team at YeeStor, a developer of memory chips and storage controllers (formerly SiliconGo Microelectronics). His team has established a set of NAND flash analytical methods, and has focused on defining new characteristics for 3D NAND. He has also been an SSD product manager at SiliconGo, and an IC design engineer at Huawei. He earned a master’s degree in microelectronics at Tianjing University (China).