Paper Title: A Low-Cost LDPC Solution for Flash Memory

Paper Abstract: We present the latest FPGA results for our multi-rate multi-length LDPC decoder for codes that have the code rates and lengths specified by IEEE P1890 Standards Working Group on Error Correction Coding for Non-Volatile Memories. The presented decoder architecture is based on the block serial layered decoder which has been widely used in high volume Hard Disk Drive (HDD) read channels. Numerous patented features of the block serial layered decoder allows at least 75% reduction in logic, memory and energy requirements compared to standard LDPC decoder architectures.

Paper Author: Osso Vahabzadeh, Staff Design Engineer, Symbyon Systems

Author Bio: Osso Vahabzadeh received his PhD in Electrical Engineering from Northeastern University, Boston, MA in 2014. His PhD work focused on low-complexity low-density parity-check (LDPC) codes. He was a recipient of Northeastern University’s Outstanding Graduate Student Award for Teaching in Life Sciences, Physical Sciences and Engineering in 2012. He joined Symbyon Systems as a Staff Design Engineer shortly after its foundation, where he has played a major role in the company’s efforts in developing error correction solutions for flash memories.