Wednesday, August 7th
|TEST-202A-1: Testing Issues (Testing Track)|
|Organizer + Chairperson: Marilyn Kushnick, R & D Engineer, Advantest|
Paper Title: Challenges of Testing PCIe Gen4 SSDs (and Beyond)
Paper Abstract: To meet the need for more storage capacity and higher data rates to support new servers and real-time big data applications, the storage industry is quickly transitioning to PCIe Gen 4 (and NVMe) as a basic SSD interface. SSD manufacturers therefore need new infrastructure and test solutions capable of validating PCIe Gen 4 devices. Challenges include higher frequencies and stricter bus timing specifications. Manufacturers will need new tools to help with everything from SSD device bring up to product launch. They will also need more capable test equipment to produce devices requiring the increased data rates and bulk test data. Understanding such difficulties aids in the testing and development of future higher speed interface technologies such as SAS-4 and PCIe Gen 5.
Paper Author: Justin Treon, Applications Engineer, Advantest
Author Bio: Justin Treon is a Staff Factory Application Engineer at Advantest, where he focuses on SSD protocol testing for SATA/SAS/PCIe/NVMe. Justin's SSD and memory-related experience includes SSD security, firmware, performance analysis, and testing and configuring memory interfaces such as DRAM, SPI, traditional NOR, and NAND flash. Justin has a total of 15 years experiences at Advantest, Micron, and Intel. He is also a specialist in embedded Linux, RTOS and scheduler-based systems with work experience in device drivers, board bring up, JTAG and UART debugging for ARM based systems, performance optimization, and memory reduction. He earned a BS in computer engineering from California State University Sacramento and has written three publications.