Paper Title: A Deep Dive into 3D NAND Silicon

Paper Abstract: We provide in-depth technical insight of 3D-NAND cell from a silicon device perspective, and offer a comprehensive view on how it relates to Flash Storage system performance and quality. We examine the physics of Program/Erase cycling stress and charge loss mechanisms in 3D-NAND devices, while providing technical insights into Threshold Voltage (Vth) degradation, RTN (Random Telegraph Noise) and device failure modes. In addition, we discuss key challenges associated with 3D-NAND scaling at >120 layers as well as key innovations that will be needed from a fab equipment/process control, wafer test, component test in order to drive strong TLC, QLC and Low Latency NAND growth in enterprise Flash Storage Systems and its applications.

Paper Author: Jung Yoon, Distinguished Engineer and CTO, Supply Chain, IBM

Author Bio: Jung Yoon is a Senior Technical Staff Member and Technology & Quality lead in IBM's Systems Supply Chain Organization. He leads a worldwide supply chain engineering team focusing on semiconductor technologies used across all IBM Systems and products. He is a recognized industry leading expert in DRAM, flash memory, SSDs, and semiconductor devices in general, and drives technology convergence between industry capabilities and IBM’s strategic product offerings. He has presented papers at many conferences including several past Flash Memory Summits. He earned a PhD in materials science from Columbia University and an MS in materials science from University of California Berkeley. He serves on Flash Memory Summit’s Conference Advisory Board and has chaired key technical sessions over the last four years.