Paper Title: Improving Waterfall Performance of low-cost FAID LDPC Decoders

Paper Abstract: The error correction requirements for the latest and upcoming memories is more and more demanding in terms of reliability and throughputs. It remains a challenge to design low cost LDPC solutions for 3D-TLC and QLC NAND controllers, that can ensure a maximum endurance for the Flash, without hurting the global latency or the power consumption. In this presentation, we present improvements of FAID technology with the main objective of improving the ECC perfomance of hard-decision LDPC decoders in the waterfall region. By doing so, we push further the need to request soft information from multiple reads of the Flash, and therefore reduce the global latency of the controller and extend the life of the device. The proposed improvements come at a negligible extra hardware complexity, and a controlled extra latency at the LDPC decoder side. We illustrate our results for error correcting codes that can enable the latest QLC Flash memories.

Paper Author: David Declercq, CTO, CodeLucida

Author Bio: David Declercq is the co-founder and CTO of Codelucida Inc. He was previously full professor at the ENSEA in Cergy-Pontoise, France, from 2001 to 2017. He is a senior member of the IEEE, and a widely renowned researcher in the area of LDPC code and decoder design. He published more than 200 papers in the area, and holds 10 patents. Several of his contributions towards LDPC code and decoder design have been employed by industry as well as adopted in several standards. He is especially recognized for his pioneering works on non-binary LDPC code and decoder designs.