Paper Title: Error Handling Technologies for QLC-Based Storage

Paper Abstract: The 3D NAND has widely adopted in the storage system for lowering the cost per bit and improving the system performance from 2017. However, due to the limitation of etching technology, the cost per bit cannot reduce linearly with the increasing of the WL stacking number. To keep declining the price of NAND Flash, 3D QLC is adopted for client SSD since 2H/2018 and It will be widely used for more and more applications like enterprise SSD/ BGA SSD/UFS/eMMC in 2019. To adopt QLC for more applications, new invented technologies are proposed for the controller design in this work, including 1) Compact RAID (C-RAID) design for DRAM less system, 2) Advanced cell-to-cell interference compensator (CTCIC) for improving the decoding capability of LDPC, and 3) temperature compensating processor (TCP) to reduce the cell deviation for widening operation temperature range of QLC. According to the experimental results, the C-RAID can achieve the same physical fail protection capability as conventional RAID architecture with 75% reduction on SRAM size, the correction capability of LDPC is 30% improved by CTCIC on QLC, and the operation temperature range of QLC can be 78% enlarged by TCP.

Paper Author: Wei Lin, System Architect, Phison Electronics

Author Bio: Wei Lin is a senior manager in Phison Electronics Corporation. He received PH.D. degree in electronics engineering from National Chiao-Tung University in Taiwan and joined Phison as consultant from 2012. He is in charge of NAND Flash characterization, design of NAND Flash architecture, and error handling for NAND Flash controllers. He has published several technical papers and more than 100 patents related to non-volatile memory.