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2:10-5:00 PM
AIML-302-1: Using AI/ML for Flash Performance Scaling, Part 2 (AI/Machine Learning Track)
Paper Title: An Analog Neuromorphic Compute System Based on SuperFlash

Paper Abstract: Current machine learning hardware is weighted towards FPGAs and GPUs and custom SoCs which can provide vast parallelization of the vector matrix multiplication (VMM) problem that is the basis for Neural Network computation. There is a parallel effort to build analog compute systems that manage VMM in the analog domain. These implementations retain the Neural Net weights in an NVM array by storing multiple bits of data per cell and using simple current addition to perform the VMM computations in the analog domain. The advantage of an analog VMM block over a comparably-performing digital implementation is significant. SST has been developing analog VMM compute capability based on our SuperFlash embedded flash technology in earnest for the last 2 years. We call this concept memBrain. The analog VMM blocks are different from the macros we have built for our many MCU customers, and have features that support the precision programming and current addition necessary to support analog VMM in production. At FMS we plan to show the history of this development, and the current market status and data to back up the production worthiness of this approach to analog compute.

Paper Author: Mark Reiten, Vice President Licensing Division, Microchip Technology

Author Bio: Mark Reiten has been an executive at Microchip corporation for the last 9 years responsible for their technology licensing business. Prior to Microchip Mark was responsible for sales at Virage Logic, a licensor of fundamental semiconductor IP who was sold to Synopsys. Prior to Virage Mark held various management roles at semiconductor and systems companies for 20 years. Mark holds a BS in Economics and a BA in Political Science from the University of Minnesota.