Paper Title: The New Generation of Storage: PCI Express 4.0 and 5.0

Paper Abstract: PCI-SIG has made huge strides to support the flash storage industry's demand for bandwidth and greater capacity. In 2017 we released PCI Express 4.0 at 16GT/s transfer rates, and in less than two years are again doubling bandwidth with the upcoming PCIe 5.0 specification at 32GT/s. In this session, we will highlight the critical PCI Express 4.0 and 5.0 advantages that position the specifications as the next generation of storage: low latency, scalability, form-factors and our robust PCI-SIG compliance program. Session attendees will learn about the current status of the PCIe 4.0 and 5.0 technology development, rollout and FYI testing.

Paper Author: Debendra Das Sharma, Chair, PCI-SIG Marketing Workgroup, Intel

Author Bio: Dr. Debendra Das Sharma is an Intel Fellow and Director of I/O Technology and Standards Group. He is an expert in IO subsystem and interface architecture, delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), coherency, multichip package interconnect, SoC, and rack scale architecture. He has been a lead contributor to multiple generations of PCI Express since its inception, a board member of PCI-SIG, and leads the PHY Logical group in PCI-SIG. Debendra joined Intel in 2001 from HP. He has a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst and a Bachelor of Technology (Hons) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur. He holds 99 US patents. Debendra currently lives in Saratoga, CA with his wife and two sons. He enjoys reading and participating in various outdoor and volunteering activities with his family.