Paper Title: Computing In Memory with tri-gate SONOS Nonvolatile Multi-level Memory

Paper Abstract: Computing in memory (CIM) is one of the most promising methods for saving energy in IoT. Important design considerations for this goal include good controllability of Vt, as well as high on/off ratio, low leakage current, and a sneak current-free architecture. We describe such a memory array architecture by using a tri-gate SONOS NVM Vt control. By controlling Vt variation to several tenths of mV/sigma, without any abnormal bits, it can provide 128 levels (7-bit precision) in one cell, with a 1000 fan in/out sneak-current-free array. The fundamental memory characteristics and performance will be presented for a device with an on/off ratio larger than 7 orders-of-magnitude and a sneak-current-tolerant structure based on dual switch transistors.

Paper Author: Yasuhiro Taniguchi, CTO, Floadia

Author Bio: Yasuhiro Taniguchi is CTO and co-founder (in 2011) of Floadia, a provider of embedded NVM design IP. Throughout his career, he developed and productized SONOS and floating gate technologies. Before Floadia, he worked in the Process Technology Development Department at Hitachi (1990 to 2003). After the merger to form Renesas Electronics, he worked as Principal Engineer at their 1st Device Development Department. Yasuhiro holds 39 US patents.