Paper Title: Non-Volatile Neural Network Accelerator in Your SoC

Paper Abstract: A cost-effective deep neural network (DNN) accelerator IP is a key building block in edge devices. Existing solution for the DNN HW typically requires off-chip access to retrieve neural network parameters from external memories, incurring additional communication latency, power consumption, and security/privacy concern. Alternative approach integrating the DNN engine in a special Non-Volatile Memory (NVM) process requires as much as 10 additional masks beyond the conventional logic CMOS process which is not cost-effective. In this presentation, we discuss the latest test chip result of our proprietary logic-compatible embedded flash based neuromorphic core which has been implemented in a 65nm standard CMOS process. The test chip result using standard CMOS technology shows good analog retention margin suitable for logic compatible non-volatile neural network accelerator. The neural network inference accuracy measured from the hardware is close to the accuracy of the software model. The maximum throughput of the core is 1.28G pixel/s and the average power consumption of a single neuron circuit is 15.9µW, achieving 171 TOPS/W with 1-bit quantization of the activation.

Paper Author: Sangsoo Lee, CEO, ANAFLASH

Author Bio: Sang-Soo Lee is CEO of Analflash, a semiconductor startup developing an energy-efficient AI chip solution for edge devices. With over 25 years of engineering and management experience in semiconductor industry, his past employment includes VP of SuVolta, VP of SK Hynix, CTO of Pixelplus, Director of LSI Logic, Design Manager at Datapath Systems, Principal Engineer at Micro Linear, and Sr. Engineer at LG semiconductor. As CTO of Pixelplus, he played a key role in taking the company to Nasdaq IPO in 2005. Sang-Soo received the PhD degree from Carnegie Mellon University.