Paper Title: Characterization of 3D NAND Flash Memories beyond 1GT/s

Paper Abstract: The request for more and more performance in SSDs is pushing Flash manufacturers to increase the I/O speed of NAND memories. Indeed, in the market we are starting to see both ONFI and Toggle NAND devices capable of running their interface beyond 1GT/s. In the near future, the transition to PCIe Gen5 will probably translate into a need for even higher speeds. From a design perspective, the most obvious consequence of high speed is signal integrity, which implies a more careful design of the entire PCB inside the SSD case. This presentation addresses another aspect: NAND reliability at high speed. As the transfer rate goes up, I/O circuits consume more power and inject more noise in the surrounding circuits; what is the impact on NAND raw BER, especially at the end of life, when distributions get closer to each other? Will high-performance SSDs have a shorter lifetime because of the speed? Could the I/O speed be a limiting factor for QLC? To answer these questions, we designed a specific NAND test flow which, together with some experimental results, is the main subject of this presentation.

Paper Author: Rino Micheloni, Fellow, Microchip Technology

Author Bio: Dr. Rino Micheloni is Vice-President and Fellow at Microsemi Corporation, where he currently runs the Flash Signal Processing Labs, with special focus on NAND Flash, Error Correction Codes, and Machine Learning. Prior to joining Microsemi, he was Fellow at PMC-Sierra, working on NAND Flash characterization, LDPC, and NAND Signal Processing as part of the team developing Flash controllers for PCIe SSDs. Before that, he was with IDT as Lead Flash Technologist, driving the architecture and design of the BCH engine in the world’s first PCIe NVMe SSD controller. Early in his career, he led NAND design teams at STMicroelectronics, Hynix, and Infineon/Qimonda; during this time, he developed the industry’s first MLC NOR device with embedded ECC technology and the industry’s first MLC NAND with embedded BCH. Dr. Micheloni is IEEE Senior Member, he has co-authored more than 70 publications, and he holds 278 patents worldwide (including 133 US patents). He received the STMicroelectronics Exceptional Patent Award in 2003 and 2004, and the Infineon/Qimonda IP Award in 2007. Dr. Micheloni has published the following books with Springer: Inside Solid State Drives – 2nd edition (2018), Solid-State-Drives (SSDs) Modeling (2017), 3D Flash Memories (2016), Inside Solid State Drives (2013), Inside NAND Flash Memories (2010), Error Correction Codes for Non-Volatile Memories (2008), Memories in Wireless Systems (2008), and VLSI-Design of Non-Volatile Memories (2005).