Paper Title: When It Comes to Emerging Embedded Memories, One-Size-Doesn't-Fit-All!!

Paper Abstract: The explosion of connected smart devices, sensor data, and on-board memory size are presenting challenges to SoC designers. Embedded systems must have optimized code and data memory architectures, while keeping power consumption, capacity, area, and cost within system requirements. Fortunately, MRAM, RRAM, and PCRAM are emerging as viable design options to provide new ways to address these tradeoffs. Design considerations affecting system optimization include different memories having different requirements in bandwidth, read/write speed, area, power (dynamic and static), reflow capable bits, endurance, retention, ECC, and BIST. Examples of the tradeoffs will be shown using Numem's IP cores.

Paper Author: Jack Guedj, CEO, Numem

Author Bio: Jack Guedj is the co-founder and CEO of Numem, a provider standard and customized MRAM-basaed IP cores for microcontrollers and SoCs. Beginning in 2008, Jack was President and CEO of Tensilica, leading it to the #1 position in merchant DSPs and, ultimately, its acquisition by Cadence in 2013. Jack was then Cadence Corporate VP, Tensilica Products. Prior to Tensilica Jack led the spin-out of Magnum from Cirrus Logic, serving as founder, president and CEO. Prior to Cirrus, he was president of Tvia, Inc., leading that company’s successful IPO in August 2000. Jack holds an MBA from the UCLA Graduate School of Management, an MSEE from Pierre & Marie Curie Engineering School of Paris, and a doctoral degree from the University of Pierre & Marie Curie