Paper Title: Enhancing TLC Flash Designs for Embedded Applications

Paper Abstract: More bits per cell in flash memory leads to higher density and lower costs. However, some characteristics, such as page read and write times, may be degraded, especially when ECC requirements are included. One way to improve the performance of TLC-based flash memory systems is to allocate a small cache and utilize it in a one-bit-per-cell mode (so-called pseudoSLC or pSLC configuration). The tradeoff is that the lifetime is reduced although it remains adequate for most applications. However, failure to design the pSLC cache properly for the intended application may cause degradation of both lifetime and performance. New methods and measures have been devised for system designers to use to achieve successful pSLC cache designs.

Paper Author: Thomas McCormick, Chief Engineer/Technologist, Swissbit

Author Bio: Thomas McCormick is currently Chief Engineer/Technologist at Swissbit, where he leads market focused R&D for product development with full life cycle support. He has over twenty years experience designing PC and embedded computer systems, including over fifteen years focused on flash memory system research and development. He holds a PhD in Computer Engineering from Northeastern University. His on-going research is focused on flash memory and next generation non-volatile memory systems for highly reliable storage in embedded applications leveraging his customer- and market-focused activities at Swissbit. He has authored numerous white papers on these topics for Swissbit as well as industry events such as Flash Memory Summit, the Embedded Systems Conference, and the Nonvolatile Memory Workshop.