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8:30-9:35 AM
NEWM-301A-1: Life Beyond Flash - New Non-Volatile Memory Technologies (New Memory Technologies Track)
Paper Title: DDR5 NVRAM: A Non-Volatile DRAM Replacement Specification

Paper Abstract: For decades, DRAM has been the staple of essentially all computer memory design hierarchies. Sandwiched between the CPU and its local caches and the bulk storage of hard drives or solid state drives, DRAM has provided a comfortable balance of performance and storage capacity. From the modest SDRAM providing 256 Mb at a bus speed of 133 Mbps, the industry is about to transition to its evolutionary derivative DDR5 with devices up to 32 Gb per die and speeds targeting 6400 Mbps. To now, non-volatile memories have not been able to achieve the full functionality of the DRAM and have been limited to a slower tier of memories called "persistent memory" or "storage class memory". Thats about to change with a new class of memories called "memory class storage". The DDR5 NVRAM specification is in process to define how memory class storage devices can not only coexist with DRAM, but they may be the logical future replacement for DRAM. This talk describes the DDR5 NVRAM specification and how non-volatile memories are being architected to emulate, and exceed, an SDRAM interface.

Paper Author: Bill Gervasi, Principal Systems Architect, Nantero

Author Bio: Bill Gervasi, Principal Systems Architect at Nantero, is a long-time prominent leader in the memory business, active since the days of 1Kb DRAMs and EPROMs. As an analyst/consultant, he has led seminars, made conference presentations, written articles, taught courses, acted as an expert witness in major patent cases, and provided comments and quotations for many industry publications. He has been very active in JEDEC, where he currently serves as Vice-Chair of the DRAM modules committee. He has served on the JEDEC Board of Directors and has chaired committees for DRAM parametrics and small form factor memory modules. He worked on the definition of all Double Data Rate SDRAMs since inception. He also helped form the JEDEC committee on SSDs and is active in the definition of NVDIMMs. Before becoming an independent analyst, he spent almost 20 years at Intel as a Systems Hardware Designer and Software Designer. He holds 10 patents in memory and packaging design. He studied computer science at University of Portland and the Oregon Graduate Center.