Paper Title: Using Functional Verification in Testing NVMe Controller Designs

Paper Abstract: Functional verification of a controller design having complex and advanced data transfer features can help catch bugs and expedite the verification process. NVMe controllers are an important current example since even basic data transfers involve command structures containing data source and target locations and the number of pages to be transferred. More complex features such as Controller Memory Buffer and Persistent Memory Region also have options to pick data, metadata, and data structures from both the host and the controller physical memory. Verification specialists will find functional verification of such controllers to be challenging, requiring a clear test plan and a model with significant flexibility. I will address the critical steps to create a verification plan and verification abilities needed by a verification component, like generating constraint random stimulus as per controller capability and check on traffic for protocol adherence for a fast signoff to functional verification of NVMe controllers.

Paper Author: Vikas Tomar, Product Engineer, Mentor

Author Bio: Vikas Tomar is a Product Engineer for NVMe and Ethernet QVIP at Mentor, where he develops verification IP. He has worked on products for PCIe, NVMe, and JTAG. Vikas has over 8 years experience in the functional verification industry. His expertise includes functional verification of bus protocols such as PCIe, and building verification environments for effective assertion and coverage based verification. He earned a B.E. in electronics and communication from the Institute of Technology and Management Gurgaon (India).