Paper Title: Using a PCIe Analyzer with NVMe-Based Products

Paper Abstract: A PCI Express analyzer can only analyze NVMe traffic as a post process, since the NVMe level must be decoded first in software. However, users need the ability to do real time analysis of NVMe products. To do that, the PCIe analysis engine must understand the NVMe command queuing mechanism and binding methods to payload. A new implementation self-learns the bindings so that it can internally separate commands from payloads, thus allowing for real time identification of performance bottlenecks and latencies. Particularly important is the ability to test the different scatter-gather list (SGL) modes that govern the data buffers. Traffic generation at the NVMe level is another key capability, including the ability to emulate an NVMe drive to present a variety of test conditions.

Paper Author: Isaac Livny, Applications Engineer, Teledyne LeCroy

Author Bio: Isaac Livny is an application engineer in the protocol systems group of Teledyne, a major analyzer maker. Isaac specializes in high speed serial protocol technology and has been following PCIe and NVMe technologies since their incubation. He is currently responsible for providing key customer solutions and support for high-speed serial protocol-based products with an emphasis on PCIe and NVMe. Isaac is a regular presenter at the PCI-SIG development conferences and played a key role in developing the UNH-IOL NVMe conformance suite. He has also been a frequent presenter at Flash Memory Summit. Before joining Teledyne, he worked at LSI and Bell Labs. He earned an MSEE from Tel Aviv University and an MBA from Montclair State University (NJ).