Thursday, December 6th
|NETW-201: NVMe-oF Reference Designs (Networking Track)|
|Organizer: Weafon Tsao, VP, AccelStorOrganizer: Ziv Serlin, VP System Architecture, E8 StorageChairperson: Vishal Shukla, Director, WW Ethernet Switch Technology, Mellanox|
Paper Title: NVMe-oF JBOF with Acceleration Capabilities
Paper Abstract: The Reference Design “NVMe-oF JBOF with Acceleration Capabilities” demonstrates a 100G NVMe-oF system solution that enables a custom accelerator for a storage array.
Paper Author: Rakesh Cheerla, Solution Planner, Intel
Author Bio: Rakesh is a Senior Product Manager for Storage Solutions at Xilinx, where he manages the product life cycle, key customer accounts, and customer deliverables. He has created a new product line to address cloud and datacenter markets, defined new product features based on customer inputs, expanded the addressable market, and driven strategic investments. He focuses on understanding customer needs, developing innovative solutions, and applying his experience in product management and engineering to meet requirements in the cloud, datacenter, telecom, and enterprise markets. Before joining Xilinx, he held management positions at CNEX Laboratories, SMART Modular Technologies, LSI, and Infineta. He has given presentations at past Flash Memory Summits and has also served as a session organizer and chairperson. He is also the co-author of a publication on NV-DIMMs. He earned an MSEE from Arizona State University and an MBA from University of Calfiornia at Berkeley.
Author 2 Bio: Gildas Genest is a Field Application Engineer for BittWare, a Molex company and FPGA hardware platform vendor. Gildas was part of the team who developed a C-to-HDL compiler for FPGAs called DIME-C in the late 2000s before FPGA vendors offered their own high level language programming tools for FPGAs. He has published articles in the field of hardware acceleration research and has a continued interest in acceleration with FPGAs and computational storage specifically.