Paper Title: Using MRAM in an Intelligent Memory Hierarchy (IMH)

Paper Abstract: STT-MRAM has been recently commercialized to simply replace e-flash as the first stage. Replacement of conventional mature semiconductor memory would not drive wider applications for new market, since it should strongly require only decrease in memory cost. Instead, this paper presents “intelligent memory hierarchy (IMH)” based on hybrid- volatile/ ”semi-nonvolatile”/nonvolatile memory (NVM) with advanced STT-MRAMs for various applications from IoT edge to Cloud. This IMH enables energy-efficient and highly reliable computing systems for each applications. Some case studies of these applications are presented in details. For example, persistent memory with embedded MRAM cache, and high-speed logging memory for SQL-data base applications. Furthermore, these features are compared between STT-MRAM, VC-MRAM and SOT-MRAM.

Paper Author: Shinobu Fujita, Senior Fellow, Toshiba Japan

Author Bio: Shinobu Fujita received PhD from University of Tokyo and joined Toshiba in 1989. He has been working for new nonvolatile memory (NVM) circuit and system designs for over 15 years. His major designs are ReRAM-based NV-logics, ReRAM-based-FPGA, NVM-based random number generators, NV-SRAM based cache memories and normally-off processors with e-STT-MRAM used from cloud computing to IoT/wearables. Currently, he is a Senior Fellow of Toshiba Corporate R&D Center, and leading a project for NVM circuit and systems for energy efficient computing with advanced VC-MRAM.