Tuesday, August 7th
8:30-10:50 AM
ARCH-101-1: Flash-Memory Based Architectures: A Technical Discussion, Part 1 (Architectures Track Track)
Organizer + Chairperson: Brian Berg, President, Berg Software Design

Paper Title: SSD Architecture Requirements for IO Determinism

Paper Abstract: Long tail IO latencies are characteristic of traditional SSDs, due primarily to flash die read operations stalling behind flash die program operations. IO Determinism provides one methodology to mitigate these long tail IO latencies by allowing application level control of data placement to avoid flash read/program conflicts. This presentation discusses current approaches to IO Determinism and how they impact and influence SSD Controller and FTL Architecture. Discussion will cover new controller features and requirements needed to effectively support IO Determinism as well as hidden challenges in supporting IO Determinism. Major topics covered: • Creating and managing variable numbers and sizes of Die Groups • Controller buffer management • FTL Impacts • Flash Management and dealing with disparate data stream velocities

Paper Author: Tim Canepa, Chief Architect and Director of Architecture, Independent Consultant

Author Bio: Tim Canepa is co-founder and CTO of a Stealth startup focused on delivering deterministic storage IO latency in multi-tenancy environments. Prior to that, Tim was Chief Architect and Director of Architecture at Seagate’s Flash Components Division where he led a team responsible for architecting Seagate’s Flash controller families. Tim came to Seagate as part of the LSI/SandForce acquisition from Avago where Tim was the director of Architecture for Flash controllers as well as co-architect of the controller family acquired by Seagate from LSI/Avago. Prior that, Tim held architecture and architecture consulting positions at a number of start-ups and large technology companies, including HP, F5 Networks, PLX Technology, Palm, Handspring, SiRF and NetFRAME. Tim has contributed to a number of different IO related standards, most notably NVMe and PCI. Tim holds a BS in computer science and a BA in business economics with honors from University of California at Santa Barbara and has over 20 patents related to solid state storage and storage interfaces.