Paper Title: Optimizing Error Recovery Flows to Minimize SSD Read Latency

Paper Abstract: In the operation of an SSD, an error recovery flow (ERF) is a collection of error recovery procedures exercised by the firmware to recover data from a noisy NVM media. It is important to optimize an ERF to ensure the reliability and influence the latency and throughput of the SSD. In each procedure of an ERF, the firmware issues read commands with certain read-reference-threshold voltages, and then drives the controller’s hardware accelerators such as an error correction decoder to correct errors. The ERFs in LDPC-based SSDs are normally more complex than those in BCH-based SSDs as firmware can choose to accumulate different granularity levels of soft information before LDPC decoding. The large number of combinations of possible error recovery procedures and their parameters such as log likelihood ratios also makes the optimization of an ERF nontrivial. In this presentation, we describe typical elements of an ERF for NAND flash SSDs and the problem of optimizing an ERF to minimize latency. We then compare the error recovery latency and reliability of an LDPC-based ERF and a BCH-based ERF under different NAND flash parameter assumptions.

Paper Author: Viet Dzung Nguyen, Senior Staff Engineer, Marvell Semiconductor

Author Bio: Viet-Dzung Nguyen has been with Marvell Semiconductor Inc. since 2013, where he is currently a DSP engineer. He received a Bachelor of Science degree in Electrical Engineering in 2007, and a Ph.D. in Electrical Engineering in 2012, both from the University of Arizona.