Thursday, August 9th
2:10-3:25 PM
INVT-302A-1: Effective Use of QLC Flash in Hyperscale Datacenters (High-Performance Computing Applications Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Dave Bursky, Technology Editor, Chip Design Magazine

Paper Title: Effective Use of QLC Flash in Hyperscale Datacenters

Paper Abstract: QLC flash is much denser and considerably cheaper than TLC flash. However, its endurance is limited to between 150 and 1,000 writes, far below the values for TLC. To take advantage of QLC as primary storage in hyperscale datacenters, its life / endurance must be increased. A novel technique called life-amplification can achieve the endurance required for a datacenter-level storage architecture. Rack-level redundancy must replace today’s conventional triple redundancy, or mirrored RAID-6, but without amplifying write operations. The amount of data to be written is reduced by global deduplication, global compression, and pattern removal to reach almost zero overhead for snapshots and clones. The management of hot and cold data must be done in a way to minimize both write amplification and the amount of overprovisioning needed. Implementing such changes will enable QLC flash to reduce storage costs significantly in hyperscale datacenters.

Paper Author: Rado Danilak, CEO, Tachyum

Author Bio: Dr. Radoslav "Rado" Danilak is the co-founder of Tachyum. He has spent more than 25 years designing state-of-the-art processing systems and delivering technically inspired, economically significant products to market. Holding more than 100 patents, Rado pioneered enterprise and consumer MLC flash adoption, with a Flash Memory Controller that increased Flash endurance (limited by device physics) by 10X. Dr. Danilak is the founder and CEO of Skyera, a supplier of ultra-dense solid-state storage systems, acquired by WD in 2014. At Wave Computing, he architected the 10GHz Processing Element of their deep learning DPU. He was cofounder and CTO of SandForce, acquired by LSI in 2011 for $377 million; a chipset and GPU architect at nVidia; a CPU architect at Nishan Systems and Toshiba; and chief architect of 64b x86 CPU at Gizmo Tech.