Paper Title: Diagnosing SSD Failures During Testing

Paper Abstract: Traditionally, ATE has focused on fault detection, i.e., apply a test, measure responses, and sort the tested devices into PASS/FAIL. System level test presents an additional challenge, i.e., fault detection is not enough and fault location is required. The test equipment must provide the means to debug and isolate a fault down to its root cause. Furthermore, fault location is required at all levels of the protocol stack, i.e., link layer, protocol layer, vendor created IP and software drivers. This challenge creates the opportunity for test equipment vendors to develop these complex and large debug and diagnosis tools and make them available to their users. Resources can be added within ATE to monitor and collect the status and traffic. Post-processing software can then sort and analyze the collected data to help determine root causes.

Paper Author: Linden Hsu, R&D Engineer Expert, Advantest

Author Bio: Linden is an R&D Engineer Expert in Advantest's System Level Test business unit. He is the FPGA lead for the PCI Express protocol and the lead for Traffic Capture and Debug Tools which help isolate the root cause of device failures on a multi-protocol SSD production tester. Before joining Advantest, he was the programmable logic design lead for LeCroy (later Teledyne LeCroy)'s Receiver Test Group. He has over 10 years experience in developing test equipment and over 25 years in the technology industry. Linden earned a BSEE from UCLA.