Paper Title: Big Data Analysis Using Hardware-Accelerated Flash

Paper Abstract: Enterprises are currently collecting huge amounts of data which they need to analyze rapidly. Since datasets rapidly exceed the DRAM capacity of even the largest affordable machines, designers need to create storage systems that can approach DRAM performance. A new system architecture achieves the required performance level by using FPGA-based hardware accelerators, large amounts of high-performance flash memory, and cross-layer optimizations. It provides the equivalent of large cluster speed and capabilities for such important applications as graph analytics and database operations (including object-based and NoSQL stores).

Paper Author: SangWoo Jun, Assistant Professor, UC Irvine

Author Bio: Sang-Woo Jun is a PhD candidate in the department of Electrical Engineering and Computer Science (EECS) at MIT. His advisor is the renowned professor Arvind, member of the National Academy of Engineering, founder of several companies, and leading researcher in computer architecture. Jun’s research focuses on making complex analytics on big data more affordable by substituting flash storage for costly DRAM and introducing reconfigurable hardware accelerators. He has published 16 articles in major conference proceedings (including the International Symposium on Computer Architecture) and in the ACM Journal of Computing Systems. Jun will be joining UC Irvine as a faculty member in the fall of 2018.