Paper Title: Ultra-Low Resource FPGA implementation of Finite Alphabet Iterative Decoders

Paper Abstract: With the rapidly growing development of flash memories based on 3D-TLC and QLC flash, the demand for powerful and low cost LDPC error correction is gaining importance, and designing low cost high throughput LDPC decoders presents a challenge. For flash controllers using FPGAs, the main bottleneck is the limited resource usage available for the LDPC decoder on the FPGA, and classical LDPC decoder solutions used in ASIC are either too large to fit on target FPGA chips, or unable to reach the NVMe throughputs. In this talk, we will discuss LDPC decoding architectures based on Finite Alphabet Iterative decoders (FAIDs) that utilize very low resource usage on the FPGA such that they can fit in any of the usually targeted FPGA chips, while reaching decoding throughputs suitable for NVMe applications. We will present synthesis results on Xilinx Ultrascale FPGA device and share size metrics for various throughputs and code parameters (rate and length). We will also present error-rate performance curves generated from FPGA simulations that show no occurrence of error floors down to frame error rate of 1e-12, both for hard-decoding and 2-bit soft-decision decoding (1-bit hard + 1-bit soft).

Paper Author: David Declercq, CTO, CodeLucida

Author Bio: David Declercq is the co-founder and CTO of Codelucida Inc. He was previously full professor at the ENSEA in Cergy-Pontoise, France, from 2001 to 2017. He is a senior member of the IEEE, and a widely renowned researcher in the area of LDPC code and decoder design. He published more than 150 papers in the area, and holds 8 patents. Several of his contributions towards LDPC code and decoder design have been employed by industry as well as adopted in several standards. He is especially recognized for his pioneering works on non-binary LDPC code and decoder designs.