Paper Title: Developing Controllers That Are Aware of Underlying NAND Structure

Paper Abstract: A single-bit program fail on a bitline may cause a controller to mark an entire block of NAND as bad. This is very wasteful, especially when the NAND technology is TLC or QLC. A new approach uses the programmable bits of a bitline, if the unprogrammable bits are tagged, Of course, it requires the NAND to expose its unprogrammable bits to its own microcontroller or even perhaps to the SSD controller. These bits can then be used to extend the lifetime and capacity of flash devices.

Paper Author: Hongjun Xue, R&D Chief Architect, UNIC

Author Bio: Hongjun Xue is the R&D Chief Architect of UNIC, concentrating on the architecture of NVMe SSDs and hardware and firmware co-design. With more than 10 years' experience in SSDs, Hongjun has a deep understanding of host-based and device-based SSD Architectures. Expertise includes NAND characterization research and flash management, such as Mapping Tables, Garbage Collection, Wear Leveling, etc.