Paper Title: An SSD Controller for 3D NAND with Compression, LDPC Coding and Media Management

Paper Abstract: An SSD Controller for High Capacity 3D TLC NAND has been designed with production-ready firmware for use in enterprise and cloud storage applications. The controller features on-the-fly data compression for improved performance, an LDPC error correction architecture with multiple code options for optimized flash flexibility and format efficiency, and adaptive media management features for flash life extension. Performance, reliability and endurance results are presented for the latest 3D TLC NAND flash memories.

Paper Author: Erich Haratsch, Director, Engineering Flash Channel Architecture, Seagate

Author Bio: Erich Haratsch is Director of Engineering at Seagate Technology, where he is responsible for the architecture of flash controllers. He leads the development of hardware and firmware features that improve the performance, quality of service, endurance, error correction and media management capabilities of solid-state drives. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in more than one billion chips. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 40 peer-reviewed journal and conference papers, and holds more than 100 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).