Wednesday, August 8th
8:30-10:50 AM
TEST-201-1: Testing/Performance Analysis (Testing Track Track)
Organizer: Joseph Chen, VP Engineering, ULINK Technolgy

Co-Organizer + Co-Chair: Easen Ho, President, S3 Metrics

Paper Title: Design Register Accurate SSD Software Simulator

Paper Abstract: One problem with designing SSD-based products is that firmware and hardware must typically be developed serially. The production firmware design can start only when the ASIC design is stable and has been synthesized in an FPGA. A new register accurate SSD simulator improves the situation. It runs on X86 and can run storage test tools such as fio and dnvme. It can hold the production firmware, so design can then begin as early as possible, even before the ASIC design code is stable. When the actual ASIC becomes available, only a short time is needed to deliver the production firmware, thus greatly reducing time-to-market.

Paper Author: Haocheng Huang, IP Design Manager, Starblaze

Author Bio: Haocheng Huang is an IP design manager at Starblaze Technology, where he focuses on SSD NVMe system, and responsible for researching and evaluating new storage technology. He has good experience on both ASIC design verification and SSD firmware design. Before join Starblaze, he was a Senior Engineer at Marvell, where he did verification and design for modem chip of LTE R11. He earned a Master’s degree in Electronic Engineering at the University of Electronic Science and Technology of China.