Thursday, August 9th
2:10-3:25 PM
CTRL-302A-1: Flash Controller Design Methods (Controllers Track Track)
Chairperson: Ludovic Danjean, Staff Engineer, Seagate

Organizer: Erich Haratsch, Director, Engineering Flash Channel Architecture, Seagate

Paper Title: Take Full Advantage of LDPC Soft Bit Decoding

Paper Abstract: LDPC is widely adopted in SSD controller due to it has good hard bit decoding capability and very strong soft bit decoding capability. LDPC soft bit decoding is very important for current 3D TLC and next generation 3D QLC with even worse bit error rate. LDPC soft bit decoding capability is decided by the number of soft bits, the Vt shift of soft bit read and the LLR mapping value of soft bit data. Good Vt shift strategy with precise LLR mapping value guarantees the bit error be corrected with less soft bit number. Our proposal takes full advantage of LDPC soft bit read. We proposed a method to do soft bit read and map the data to corresponding LLR which will speed up the flash read error handling.

Paper Author: Licheng Xue, Sr. Staff Engineer, Starblaze

Author Bio: Lecheng received a CS PhD degree from Beijing Institute of Technology. Currenty working at Starblaze as a Sr. Staff Engineer. The focus is on LDPC and flash charactering.