Paper Title: 3D NAND Flash Cell Architecture: Recent Progress and Comparisons

Paper Abstract: All major flash manufacturers are producing up to 64- or 72-layer 3D NAND. Recent progress in 3D NAND cell architectures from the major 3D NAND players will be updated from FMS 2017. We are expecting 96-layer products this year. Technology barriers and challenges for 3D NAND process integration will be explained, such as very high aspect ratio, channel and source contact formation, charge leakage from the trap layer, forming staircase/word line pad connection, and multi-stack cell architecture. Unique and detailed cross-section photos will be shown of the major NAND chips. We will explore many questions regarding the next 3D NAND architectures, such as: How many cells can be stacked? NAND cell current? Decoder/selector reliability and controllability? Electron migration in charge trap layer? Cell and memory peripheral design? Future challenges and predictions of new developments will be presented.

Paper Author: Jeongdong Choe, Consulting Engineer, TechInsights

Author Bio: Dr. Jeongdong Choe is a trusted subject matter expert on memory products as a senior technical fellow at TechInsights. He has 27+ year professional on cutting-edge manufacturing technologies on semiconductor products including DRAM, 2D/3D NAND FLASH, SRAM/Logic and emerging memory such as STT-MRAM/PCRAM/ReRAM/FeRAM and 3D XPoint Memory. Jeongdong Choe worked for SK Hynix and Samsung Electronics for over 20 years. He is an author of over 100 US filed patents, manufacturing expertise in high technologies including direct experience on semiconductor process and device integration, memory cell design, and unit process development. He has been doing technical research, analysis and consulting on semiconductor memory products/ process flow, device integration, technology roadmap, landscape and cost analysis including 2D/3D NAND, DRAM, Emerging Memory, 3D XPoint, Package, TSV (HBM, HMC, Wide IO), and Processor/Logic technology at TechInsights.