Tuesday, August 7th
8:30-10:50 AM
ARCH-101-1: Flash-Memory Based Architectures: A Technical Discussion, Part 1 (Architectures Track Track)
Organizer + Chairperson: Brian Berg, President, Berg Software Design

Paper Title: A Machine Learning Framework for NAND Flash Lifetime Extension

Paper Abstract: The advent of 3D Flash Memories has radically changed the way data reliability is managed inside Solid-State Drives (SSDs). Adding the third dimension to the manufacturing process exponentially increased the number of variables controlling how data are written, erased and read. As a consequence, flash management algorithms are now becoming a big deal and more and more computational resources are required inside the SSD controller. Moreover, keeping as low as possible the Raw Bit Error Rate (RBER) over the drive's lifetime is a must have since too frequent errors corrections or even error recovery operations severely impact the SSD Quality of Service (QoS). In this work a machine learning framework for NAND flash lifetime extension is presented. Basically, the idea of the proposed approach is to predict the reliability behavior of the target memory by leveraging machine learning algorithms trained on previously collected characterization data. The result of this process is a set of compact models that can be implemented either in firmware or in hardware helping the SSD controller to make real-time decisions aimed to reduce the RBER while keeping a good QoS.

Paper Author: Lorenzo Zuolo, Flash Engineer, Microsemi

Author Bio: Lorenzo Zuolo received the M.Sc. degree in Technology for Telecommunications and Electronic Engineering, and the Ph.D. in Engineering Science from the University of Ferrara in 2012 and 2016, respectively. From 2016 to 2017 he held a Research Assistant position with the Engineer department of the same institution working on architectural/physical simulation of Solid State Drives (SSD) and emerging non-volatile memories. During the same period, he has been also CTO and co-founder of SSDVision, a start-up focused on the development of CAD tools for the design and performance evaluation of SSDs. Since June 2017 he is holding the Flash engineer position at Microsemi Corp working on efficient Error Correction Code strategies and Machine Learning algorithms for NAND flash based SSDs.