Paper Title: Fully Integrated LLR Calculation Flow

Paper Abstract: In the last decade the data production growth rate increased exponentially. Thanks to the ubiquitous exploitation of IoT devices, real-time security systems, and autonomous cars, it is estimated that by 2025 the worldwide data will reach 163 ZBytes. At the same time, realtime analytics applications are shifting the usage model for stored data from “long-term archival” to “ready-to-be-processed”. To face the relentless need for speed and storage capacity, cloud providers are now adopting hundreds of PCI-E NAND flash-based Solid-State Drives (SSDs). At the same time, NAND Flash vendors are increasing year-by-year the capacity of flash memories and today it is common to store up to 1Tb in a 18x12 mm package. Such storage density increase, however, led to a reduction of the data reliability of flash memories and hence that of SSDs. With this respect, it is now common to have SSD controllers with powerful Error Correction Codes such as Low-Density-Parity-Check (LDPC). In this work a fully-integrated LDPC-LLR calculation flow is presented. Optimized LLR tables can be computed for different customers depending on the usage model and reliability requirements in a complete autonomous way.

Paper Author: Lorenzo Zuolo, Flash Engineer, Microsemi

Author Bio: Lorenzo Zuolo received the M.Sc. degree in Technology for Telecommunications and Electronic Engineering, and the Ph.D. in Engineering Science from the University of Ferrara in 2012 and 2016, respectively. From 2016 to 2017 he held a Research Assistant position with the Engineer department of the same institution working on architectural/physical simulation of Solid State Drives (SSD) and emerging non-volatile memories. During the same period, he has been also CTO and co-founder of SSDVision, a start-up focused on the development of CAD tools for the design and performance evaluation of SSDs. Since June 2017 he is holding the Flash engineer position at Microsemi Corp working on efficient Error Correction Code strategies and Machine Learning algorithms for NAND flash based SSDs.