Paper Title: A 4KB-codeword LDPC ECC engine with advanced DSPs for enterprise SSD

Paper Abstract: With declining of NAND Flash price, 3D NAND Flash memory is becoming the majority in SSD shipment and the expected YoY of enterprise SSD is more than 150 % in 2018. To have better QoS of enterprise SSD, a 4KB-codeword LDPC ECC engine with advanced digital signal processors are proposed in this work. The equivalent correction capability of hard decoding and soft decoding achieves 107bits/1KB and 237 bits/1KB, respectively. Moreover, 1) self-tracking read level optimizer, 2) ML based reliability information processor, 3) HRE compensation processor are proposed to reduce the retry read trigger rate, soft decoding trigger rate, and RAID ECC trigger rate. According to the experimental results with 3D TLC NAND based storage system, the retry read trigger rate of can be reduced from 1 to 0.00001 at EOL (10K PE cycles and 1 month retention time) without extra read operation by the proposed ECC engine and DSPs.

Paper Author: Wei Lin, System Architect, Phison Electronics

Author Bio: Wei Lin is a senior architect in Phison Electronics Corporation. He received PH.D. degree in electronics engineering from National Chiao-Tung University in Taiwan and joined Phison as consultant from 2012. He is in charge of NAND Flash characterization, design of NAND Flash architecture, and error handling for NAND Flash controllers. He has published several technical papers and more than 100 patents related to non-volatile memory.