Paper Title: A Low-Cost LDPC Decoder for Flash Memory

Paper Abstract: Abstract. We report FPGA implementation and frame error rate results for our multi-rate multi-length LDPC decoder for codes that have the code rates and lengths specified by IEEE P1890 Standards Working Group on Error Correction Coding for Non-Volatile Memories. The presented decoder architecture is based on the block serial layered decoder which has been widely used in high volume Hard Disk Drive (HDD) read channels. Numerous patented features of the block serial layered decoder allows at least 75% reduction in logic, memory and energy requirements compared to standard LDPC decoder architectures.

Paper Author: Osso Vahabzadeh, Staff Design Engineer, Symbyon Systems

Author Bio: Osso Vahabzadeh is a Staff Design Engineer at TexasLDPC Inc. He received his PhD in Electrical Engineering from Northeastern University, Boston, MA in 2014. He was a recipient of Northeastern University’s Outstanding Graduate Student Award for Teaching in Life Sciences, Physical Sciences and Engineering. He is currently focused on developing error correction solutions for flash memories.