Wednesday, August 8th
8:30-10:50 AM
CTRL-201-1: Controllers and Flash Technology, Part 1 - Hardware and Algorithms (Controllers Track Track)
Chairperson: David Declercq, CTO, CodeLucida

Organizer + Instructor: Erich Haratsch, Director, Engineering Flash Channel Architecture, Seagate

Paper Title: Beyond AWGN, Soft Decoding performance Optimization for Flash Channels

Paper Abstract: Soft input decoding is used in modern SSDs to improve error correction performance and extend the lifetime of a drive. Soft decoding involves performing multiple reads from the Flash and combining these different reads to create Soft input values that decoders such as LDPC can use to significantly improve error correction performance compared to single-read decoding. Soft decoding presents several challenging issues such as choosing how many re-reads to perform, choosing the correct type of re-reads and creating the correct soft value mapping table for the collected information. Additionally, Modern Flash channels have an Additive White Gaussian Noise (AWGN) component but also include a Uniform Noise (UN) component and High Reliability Errors (HREs). A re-read optimization strategy is described and LDPC soft input error correction performance is presented for several different channel conditions where each channel is defined as a different mix of Gaussian, Uniform and HRE noise. Error Correction performance over each of these channels is compared to understand the impact of UN and HREs on Soft Decoding operation and the lifetime of SSD drives.

Paper Author: Peter Graumann, Technical Director, End Point Solution Business Unit, Microsemi

Author Bio: Peter Graumann is a Technical Director with Microsemi in charge of Flash Error Correction Architectures and Implementation. He has 25 years of experience in high-speed Digital Signal Processing applications, including Wired and Wireless Phy architectures, Error Correction solutions and High-speed Serdes designs. He has developed Phys for standards such as WiGig, LTE and WiMax and FEC solutions covering everything from BCH and RS decoders to Infinitely interleaved codes, Turbo codes and many generations of LDPC solutions. Peter obtained a Masters in Electrical Engineering from the University of Calgary on the topic of Silicon Compilation and holds over 25 Digital Signal Processing patents.