Paper Title: Horizontal Error Detection & Vertical LDPC ECC for Reliable 3D-TLC NAND Flash

Paper Abstract: 3D triple-level cell (TLC) NAND flash memories achieve large capacity by storing 3 bits per cell. However, the reliability of TLC NAND flash is degraded due to the narrow read VTH margins between each VTH-state [1]. To enhance the reliability of NAND flash, Asymmetric Coding (AC) has been proposed [2-3]. Moreover, low-density parity-check (LDPC) error correcting code (ECC) achieves high error correcting capability. LDPC ECC requires predicted bit-error rate (BER) information for each bit [4]. Error correcting capability of LDPC ECC depends on the accuracy of BER prediction. Based on AC and LDPC ECC, this paper proposes two techniques [5]. First, Horizontal Error Detection (HED), which includes AC algorithm, detects errors and increases predicted BER for cells where errors have been detected, and improves error correcting capability of LDPC ECC. Second, Vertical-LDPC (V-LDPC) modifies the coding method of LDPC ECC to eliminate the difference of detected error rate among TLC three pages, and improves the worst reliability page in each word-line. By combining HED with V-LDPC, the data-retention time and acceptable BER are increased by 230% and 90% in 3D-TLC NAND flash, respectively.

Paper Author: Shun Suzuki, Student, Chuo University

Author Bio: Shun Suzuki received the B.E. degree in 2018 from the Department of Electrical, Electronic, and Communication Engineering, Chuo University, Tokyo, Japan, where he is currently working toward the M.S. degree. He has been engaged in research on reliability enhancement techniques for NAND flash memory-based SSD.