Paper Title: Generalized Tree Architecture with High-Radix Processing for an SC Polar Decoder

Paper Abstract: This study presents the design of an efficient architecture for the SC polar decoder. The proposed architecture is designed based on the conventional tree architecture with the multibit decoding and the overlapped scheduling, but the architecture is generalized considering the high-radix processing, wherein several successive radix-2 kernels are processed within a cycle. The complexity and the throughput are formulated for the generalized tree architecture based on the high-radix processing, and the design parameters are found to achieve a high throughput and/or a low complexity. A 1024-bit SC decoder is designed based on the proposed architecture in 0.18um CMOS technology; its throughput is 640 Mbps for the rate-1/2 code, and the complexity is 271K in terms of the equivalent gate count. The figure of merit of this decoder is 4.9 times that of the previous state-of-the-art SC decoder. Although the efficacy of the proposed architecture has been substantiated by a sample design for the SC decoder aiming at a high throughput and a low complexity, it is possible for the proposed architecture to be employed with different objectives to design a component for more advanced decoders.

Paper Author: Taehwan Kim, Professor, Korea Aerospace University

Author Bio: Tae-Hwan Kim received the B.S. degree in electrical engineering from Yonsei University, Seoul, Korea, in 2005 (with high honors), the M.S. and Ph. D. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejon, Korea, in 2007 and 2010, respectively. In 2010, he received ``Best Paper Award" for his Ph.D. dissertation. From 2010 to 2011, he worked for Samsung Electronics as a senior research engineer, in charge of R\&D on the baseband systems for Wi-Fi. On Oct. 2011, he joined the faculty of School of Electronics, Telecommunication and Computer Engineering in Korea Aerospace University. His current research is focused on the VLSI architectures for signal processing systems.