Paper Title: Artificial Neural Network Coupled LDPC ECC for 3D-NAND Flash Memories

Paper Abstract: 3D-NAND flash has novel, complicated error sources that call for advanced solutions. In 3D charge trap flash, variation of the diameter of the cylindrical channel among word-lines, complicated inter-word-line variations, vertical charge de-trapping causing cell Vth shift, and charge loss due to lateral charge migration all can cause errors. In floating-gate 3D NAND, error mechanisms also include charge de-trapping and inter-floating-gate capacitive coupling. To solve these reliability problems, this presentation introduces an Artificial Neural Network (ANN) coupled LDPC ECC (ANN-LDPC ECC) to adaptively and automatically correct errors. Competing approaches typically involve long training periods and address only fixed error sources, such as capacitive coupling. Our ANN-LDPC approach monitors the actual BER of the cells as they wear and retain data and adapts the LDPC code to the current conditions. This method saves time and table storage area. It is shown to increase the acceptable BER by 2.5 and 2-times compared with BCH ECC in charge-trap and floating-gate 3D-NAND flash, respectively. Furthermore, we will show a detailed block diagram of the system and describe our design methodology for the ANN.

Paper Author: Toshiki Nakamura, Student, Japan/Chuo University

Author Bio: Toshiki Nakamura received the B.E. degree in 2017 from the Department of Electrical, Electric, and Communication Engineering, Chuo University Tokyo, Japan, where he is currently working toward the M.S. degree. He has been engaged in a research on reliability of NAND flash memories.