Paper Title: Reducing Performance Variations Caused by Garbage Collection in Enterprise SSDs

Paper Abstract: All data centers want predictable performance - it is particularly important in clouds that want to maximize revenue. However, SSD performance varies depending on how much time has to be spent on garbage collection (GC) during a particular period. One approach to evening out the effects involves formulating a stochastic optimization model that characterizes the nature of GC processes and considers both total GC counts and GC distributions over time. Based on the optimization model, an innovative self-adaptive GC strategy has been developed that evenly distributes GCs for enterprise SSDs. The design reduces performance fluctuations and ensures the steady I/O performance that is critical to data centers. The key insight behind the approach is that the number of invalid pages is a finer-grained metric of triggering GCs than the number of free blocks. Evenly distributing GCs despite changing I/O patterns substantially reduces I/O blockages and latency due to GCs. Extensive experiments using traces from practical applications show that the design reduces the total GC counts by 70% and GC variance by up to 57%, compared to the state-of-the-art GC algorithms. Such improvement is even more pronounced for I/Os with data locality and burstiness.

Paper Author: Ken Qing Yang, Professor and CSO, University of Rhode Island and Dapu Microelectronics Ltd CO

Author Bio: Ken Qing Yang is an IEEE Fellow and a Distinguished Engineering Professor in the Department of Electrical, Computer, and Biomedical Engineering at the University of Rhode Island, where he has been a faculty member since 1988. He is a director of the High Performance Computing Lab (HPCL) at URI and is a recipient of several university accomplishment awards. His research interests include computer architecture, memory and storage systems, computer networks, embedded computer systems and applications in neural-machine interface and biomedical engineering. He has published over 100 technical articles in these areas and holds over 25 issued patents plus 12 pending ones. Most of his patents have been licensed to computer industry with significant practical impact, and four high tech startup companies have been formed based on them. His latest startup VeloBit, based on I-CASH architecture, was acquired by Western Digital. He is currently Chief Scientific Officer of Shenzhen Dapu Microelectronics which he co-founded with his former students and other research scholars. He earned a PhD in electrical engineering from the University of Louisiana, Lafayette.