Paper Title: Designing Enterprise Controllers with QLC 3D NAND

Paper Abstract: The search for higher NAND densities has led to widespread use of multilevel cells containing multiple data bits. Density goes up, but reliability and endurance decrease and latency increases.QLC 3D NAND is the latest such approach, now with 4-bit cells. Controllers must cope with about 5x lower endurance than TLC and much longer programming times. Read disturb and retention become more pronounced, particularly with increasing wear, and require more complex error mitigation and more internal data relocations.Tradeoffs in controller design change greatly, and designers must consider workload-adaptive solutions. New data placement options and new garbage collection and wear-level algorithms are also essential for enabling QLC in enterprise storage.

Paper Author: Roman Pletka, Research Staff Member, IBM Zurich Research Lab

Author Bio: Roman Pletka is a research staff member and master inventor for cloud storage and analytics at the IBM Zurich Research Laboratory where he focuses on non-volatile memory technologies in storage systems. He has published 20 articles and obtained over 70 patents in security, scalability, and availability of distributed storage systems as well as quality-of-service in high-speed networks, active networks, and network processors. He has made presentations at many international conferences including the ACM International Conference on Systems and Storage (SYSTOR) and the Nonvolatile Memory Workshop. He has over ten years experience in storage systems research. He earned a PhD in computer networking from ETH Zurich, Switzerland and an MS in the same subject from EPFL (Swiss Federal Institute of Technology of Lausanne).