Thursday, August 9th
8:30-10:50 AM
CTRL-301-1: Flash Controller Design Options (Controllers Track Track)
Chairperson: Roman Pletka, Research Staff Member, IBM Zurich Research Lab

Organizer: Erich Haratsch, Director, Engineering Flash Channel Architecture, Seagate

Paper Title: A New Circuit Level Controllable SSD Emulation System

Paper Abstract: During controller development, designers want to determine if their ECC algorithm will work on a variety of NAND technologies. After all, the technology in use today may be superseded quickly due to technical advances, supply issues,or pricing problems. A new emulation system can help with the testing process. It can provide access to a variety of NAND types, and can support ONFI and TOGGLE interface protocols. It can also simulate the error bit distribution of NAND under various P/E cycles andretention values. The emulation is a self-learning system, designed using a deep learning algorithm, so it canreadily be extended to new technologies as well. It is thus a valuable tool in evaluating ECC algorithms and selecting the best one.

Paper Author: Lihua Sun, R&D Chief Architect, UNIC

Author Bio: Lihua Sun is a Firmware Manager at UNICē Memory Technology, where he focuses onsystem data path optimization for flash controllers. His specialties include NAND flash interfacesand characterization. He previously workedfor Mediatek, Greenliant, Memblaze, and Dera Storage, developing products suchas USB flash disks, eMMC based systems, and NVMe SSDs. He has 10 years of SSD R&Dexperience. He earned a Master’s Degree in microelectronics and solid electronics from Beijing University of Technology.