Wednesday, August 8th
3:20-5:45 PM
NVME-202-2: PCIe/NVMe Storage (NVMe Track Track)
Co-Organizer: Deepankar Das, CTO, Sureline Systems

Organizer + Chairperson: Rakesh Cheerla, Solution Planner, Intel

Paper Title: Reconfigurable Compression Engine for NVMe-Based Storage Systems

Paper Abstract: Data compression is a key element in today's data centers because it reduces demand for storage and network bandwidth, thus lowering costs and increasing throughput. However, the compression itself may take a large amount of CPU time. One way to reduce the overhead is to add an offload engine. Obviously, the engine must be high-performance, easy to interface to existing systems, and relatively inexpensive. The best solution is to make it FPGA-based, since the latest devices are very fast, have extensive development support, and can easily handle popular compression algorithms. A typical example is a GZIP/ZLIB/Deflate compression offload engine capable of processing more than 1 GB/s. The device operates as an NVMe namespace, allowing simple communications as a block device or via a memory-mapped internal buffer using the inbox NVMe driver. Performance results show the value of the engine in a wide range of NVMe applications.

Paper Author: David Sloan, Software Engineer, Eidetic communications

Author Bio: David Sloan is a Software Engineer at Eideticom, a developer of systems and software for advanced storage applications. At Eideticom, he has worked on the development of an FPGA-based accelerator for NVMe-based systems. His duties include scaring away monster squirrels, pouring authentic Canadian maple syrup on the keyboards of delinquent programmers, and being sure that all Canadians remain unmemorable (as referenced in the Doonesbury comic strip). He is currently completing his PhD at the University of Alberta, where he has worked on integrated circuit design and system integration. He earned a BSc in computer engineering from the University of Alberta.