Paper Title: An NVMe-based FPGA Storage Workload Accelerator

Paper Abstract: FPGA-based storage acceleration promises the capability to offload the host CPU for processing intensive tasks such as error protection and compression. By leveraging the NVMe specification to provide access to storage acceleration functions, existing out-of-box drivers and storage tools can be used to test, benchmark, and deploy the accelerator card. We describe the design and testing challenges of implementing a firmware programmable NVMe controller for acceleration on an FPGA acceleration platform. The architecture of the implementation of the NVMe controller is described, including the design tradeoffs required to achieve the desired throughput and latency performance. We discuss the advantages of advanced NVMe features, such as Controller Memory Buffer (CMB) and Scatter-Gather Lists (SGLs), for use in acceleration offload.

Paper Author: Sean Gibb, VP Software, Eideticom

Author Bio: Sean Gibb is a software professional with over 20 years of experience initiating and leading complex software development projects. Before founding Eideticom, he was Lead Software Engineer at PMC-Sierra where he performed software system and algorithm development of LDPC FEC/ECC for enterprise-grade SSD controllers. Before joining PMC, he was a founder and Director of Software at Rad3 Communications, a Senior Staff Engineer at Nextwave Wireless, and a digital IC designer at SiWorks. He is an expert on algorithm acceleration and implementation of algorithms on multi-core processors and other programmable platforms. Sean is an author of several novel patents on FFT architectures and holds a PhD in electrical engineering from the University of Calgary where he specialized in the automatic generation of application specific processors.