Paper Title: 3D NAND Technology Scaling Helps Accelerate AI Growth

Paper Abstract: 3D NAND technology scaling will help drive accelerated growth of AI by providing high throughput density, lower power consumption, and smaller system footprints. Such scaling enables multiterabit TLC and QLC densities through cell layer count increases, as well as innovations in circuit design, process technology, and stacked packaging. The resulting cost reductions, throughput increases, and lower power consumption are critical to flash driven AI growth. There are further challenges associated with 3D NAND scaling at > 100 layers, cell structures (such as charge trap or floating gate), materials, and fab equipment/process controls. Density, performance, and reliability tradeoffs must be considered for TLC, QLC, MLC, and low latency NAND. High density stacked packaging for driving high throughput data ingestion and system reliability requirements for AI optimized workloads must also be improved.

Paper Author: Jung Yoon, Sr Technical Staff Member - Silicon Technology & Quality, IBM Procurement Engineering

Author Bio: Jung Yoon is a Senior Technical Staff Member and Technology & Quality lead in IBM's Systems Supply Chain Organization. He leads a worldwide supply chain engineering team focusing on semiconductor technologies used across all IBM Systems and products. He is a recognized industry leading expert in DRAM, flash memory, SSDs, and semiconductor devices in general, and drives technology convergence between industry capabilities and IBM’s strategic product offerings. He has presented papers at many conferences including several past Flash Memory Summits. He earned a PhD in materials science from Columbia University and an MS in materials science from University of California Berkeley. He serves on Flash Memory Summit’s Conference Advisory Board and has chaired key technical sessions over the last three years.