Paper Title: The Reality of an NVMe IO Deterministic Drive Using QLC

Paper Abstract: Last year's FMS conference showed how flash array isolation using a single controller offered the a 50x read latency improvement in a multi-tenant environment. The NVMe committee over the last year has worked hard to create a standard around such a concept and in this year's paper we'll explore Toshiba's first implementation of the IO Determinism standard and the challenges along the way that were addressed to create a fundamentally new storage architecture for NAND flash devices. QLC flash memory creates unique challenges, and we will explore the potential in improving read latency by more than 50x.

Paper Author: Steven Wells, Fellow – SSD Data Center Architecture, Toshiba

Author Bio: Steven Wells is a Fellow leading SSD data center architecture at Toshiba. Involved in the flash industry for over 30 years, Wells presented the first SSD that included garbage collection, wear leveling, and defect management at the International Solid State Circuits Conference (ISSCC) in 1993. He has worked on over 10 SSD designs ranging from enterprise to low power client and has received over 50 patents in solid state storage. He has presented at many conferences including Flash Memory Summit, Intel Developers Forum, and ISSCC. He holds a bachelor’s degree in electrical engineering and computer science from the University of Colorado at Boulder.