Paper Title: LDPC Codes Expand Enterprise-Level Reliability

Paper Abstract: Error handling capability becomes more essential than ever with the emergence of QLC NAND, open-channel SSD, telematics, and other enterprise-level applications. When looking for possible solutions that can provide not only strong endurance/retention support for 3D/QLC NAND, but also the data integrity for database/enterprise services, all the answers lead to a reliable error correcting code. The increasing reliability of ECC also helps reduce cost that comes from expensive system-level recovery mechanism such as RAID or read-retry. While the industry common requirement of enterprise ECC is 1e-16 UBER (user bit error rate), we will go to discuss the reliability beyond 1e-16 and the error behavior in this region in this presentation. A comprehensive LDPC design flow containing decoding mechanism, error-floor prediction and code optimization will be introduced.

Paper Author: Shiuan Hao Kuo, Supervisor Engineer, Silicon Motion

Author Bio: Shiuan Hao Kuo is a supervisor engineer at Silicon Motion, where he focuses on algorithm research of LDPC code. He is the developer of low power/low area 4K-LDPC algorithm and SMI’s low-power 3rd generation encoder. He is also in charge of several research projects including rate-compatible LDPC code design, error-floor behavior analysis and advanced object storage. He holds a PhD in error correction coding from National Taiwan University (Taiwan) and an MSEE from National Tsinghua University, Taiwan.