Paper Title: Using Software to Reduce High Tail Latencies on SSDs

Paper Abstract: Common storage workloads such as key-value stores are latency sensitive but generate block I/O patterns that may introduce high tail latencies on NAND SSDs. Strategies for reducing them may involve software, system configuration, and new features defined in the NVMe specification. Insight from empirical data has led to three approaches to minimize tail latency outliers and achieve a desired upper bound on read latency (often referred to as IO determinism) for latency sensitive workloads. The first approach involves software algorithms that span a collection of SSDs. They use the IO determinism capabilities slated for the NVMe 1.4 spec, namely Sets and Deterministic/Non-deterministic (D/ND) Windows. For SSDs that lack such capabilities, a second approach uses IO shaping techniques to deliver desired QoS while guaranteeing a minimum write bandwidth. A third approach involves advanced buffering algorithms using 3D XPoint technology. Test results show latency dropping from tens of milliseconds at the 99.99 percentile to under a millisecond for such approaches.

Paper Author: Kapil Karkra, Software Architect, Intel

Author Bio: Kapil Karkra is a Principal Engineer and the lead software architect in Intel’s Nonvolatile Memory Solutions Group responsible for the architecture of Virtual RAID on CPU (VROC), Volume Management Device (VMD), NVMe, and Caching Acceleration Software (CAS) drivers. He also leads host software advanced development activities. Kapil actively drove the latest proposal for enclosure management (NPEM) in the PCIe base specification for the NVMe ecosystem. His current focus is around improving IO determinism through software approaches and utilizing the benefits of collections of drives. Kapil has spent his entire career advancing storage architectures (e.g., RAID, caching, and storage interfaces) at companies like IBM, Philips, and Intel. He has over 20 years of storage experience and holds two patents with seven more pending. He actively participates in standards committees such as NVMe and PCIe. Kapil holds a bachelor’s degree in Electrical Engineering from National Institute of Technology (NIT) in India and an MBA from Arizona State University.