Paper Title: Improving 3D NAND Technology Scaling by Meeting Channel Hole Process Challenges

Paper Abstract: Channel hole patterning is among the most challenging processes in 3D NAND due to the extremely high aspect ratio (HAR) features with values over 50:1. Such high values make it difficult to maintain a uniform hole diameter from the top to the bottom of the film stack, which is necessary to minimize channel bowing and twisting. The resulting non-uniformity often leads to shorts or interference between neighboring memory strings. Current industry carbon masks have major limitations when extended to thicker channel hole stacks. New high selectivity masks can perform much better, but raise open challenges for integration into the overall channel. Meeting those challenges leads to higher density via innovative deposition and etch solutions, thus making larger devices possible without any other changes and further enabling the 3D NAND bit cost scaling roadmap.

Paper Author: Bart van Schravendijk, Fellow, R & D Division, Lam Research

Author Bio: Bart van Schravendijk is currently Chief Technical Officer, Dielectrics at Lam Research Corporation, Fremont, CA, USA. At Lam, he is focused on emerging technologies in the dielectric deposition area. In recent years these have found their application in VNAND, MRAM and Phase Change memories. He has 30+ years of experience in wafer fabrication equipment development, process technology and process integration. He has authored over 90 patents and numerous publications.