Paper Title: Measuring 3D TLC Voltage Distributions and Optimized Read Threshold Calibration

Paper Abstract: On the back of market-ready 3D NAND, storage devices are getting bigger and faster. However, will they get more reliable? Out-of-the box data retention quality for many 3D NANDs is just not good. When this high stress data retention environment bites, we need to massage the NAND's pre-set read thresholds to improve the quality of data emerging from the NAND. The presentation is an informative introduction to a methodology for optimally calibrating a NAND flash memory's read threshold registries. I will detail a simple method to quickly and accurately obtain NAND flash memory voltage distributions in FPGA/hardware by incrementing read thresholds and measuring wordline error statistics. I will present and compare real 3D TLC NAND voltage distributions showing how they change with increases in PE cycles and data retention. I will compare the voltage distributions from different layers in the 3D stack and comment on the similarities and differences between them. In the case of a vendor using a multi-pass programming algorithm, I will show that similar to 2D technologies, this causes a multi-modal effect on the voltage distribution and comment on the challenges this poses to error correction. I will show how the extracted voltage distribution can be used to calibrate the NAND's hard/soft read threshold registries and demonstrate both the improvement in the NAND's data quality arising from this calibration and that BCH and LDPC ECC can reliably retrieve data in high stress data retention environments when before the calibration it could not.

Paper Author: Oliver Hambrey, Research Engineer, Siglead

Author Bio: Oliver is the lead research engineer at Siglead Europe Limited based in Coventry, UK. Oliver's education is in mathematics and he obtained a Masters of Mathematics degree from the University of Warwick in 2007. Oliver joined Siglead Europe in 2010 after a successful collaboration with them whilst working towards his MSc in Complexity Science, also obtained from the University of Warwick. Oliver is key in the development of DSP and ECC for Siglead's SSD controller, but also develops DSP solutions outside of flash memory, such as low-complexity detectors and decoders for two-dimensional magnetic recording.